switch-to-CPU interface

Reading Rich Seifert's "The switch book", I got confused. At one moment Mr. Seifert writes that normally there are two interfaces CPU-to-switch: one is simply control interface to read/write the switch's registers and tables and the other one is data path, which is usually implementation specific, i.e. it may be PCI, DMA or some proprietary interface. That's fine, it makes sense.

Later in the chapter about building the switch, the author says that *for convenience* the data interface between the switching hardware and housekeeping microprocessor is often implemented as a port, i.e as I see it the CPU borrows one port from the switch. And I often see that a lot of Layer 2 switches out there exploit exactly this strategy -- dedicate one port for CPU (for example, 8FE + 3GE switch will use one GE to wire up with the processor, ending up 8FE+2GE device).

So, it appears that there are more then *two* interfaces -- one for control, and two for data?

It is very likely that I misread the text, so I'd be thankful to anyone who would help me to understand the issue.

I am not referring to a second data port, just one data port and one control port. The data port is implementation-specific, i.e., it can be a standard interface or some proprietary (e.g., internal bus) interface. To allow off-the-shelf microcontrollers to be used with a given switching chip, it is common practice to make the CPU-to-Switch Data Interface simply be one of the high-speed ports, as you noted. Thus, the data port may be a standard GE interface between a commodity switching chip and a commodity microcontroller that already has an Ethernet port built in. In other implementations, the switch-to-CPU port might be a parallel, memory-style interface; this would be more likely in a CPU/Switch combination that was specifically designed to be used as a pair.

I hope this helps!

-- Rich Seifert Networks and Communications Consulting 21885 Bear Creek Way (408) 395-5700 Los Gatos, CA 95033 (408) 228-0803 FAX

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