Question about 802.3 clause 24 - Transimit/Transmit-Bits state diagram

Sep 12, 2007 2 Replies
S

Hi,



I have a very specific question about 802.3 clause 24 state diagram. In Figure 24-7, Transmit Bits state diagram, looks like the state transition happens every 8ns without interruption.



In Figure 24-8, Transmit state diagram, after "START STREAM K" state, we need to start assigning ENCODE(TXD) data to tx_bits[4:0] in "TRANSMIT DATA" state. However, there is a extra latency for "ERROR CHECK" in between that interrupts the "parallel-to-serial" function.



Could anyone explain to me because maybe I misunderstand the state diagram? Thanks a lot.



Best regards, Joseph



Vote
Twitter Facebook LinkedIn
R

There is no "latency" (i.e., time delay) introduced by the ERROR CHECK state. Section 24.4.7 (State Diagram Conventions) notes that the state diagrams in Clause 24 follow the conventions of 21.5. Section 21.5.1 states that "actions inside a state block execute instantaneously." That is, the state diagrams describe *functional behaviors*; they are not flow charts for an implementation. By "instantaneously", we mean that the actions occur much faster than external events, such that they incur no significant latency.

-- Rich Seifert Networks and Communications Consulting 21885 Bear Creek Way (408) 395-5700 Los Gatos, CA 95033 (408) 228-0803 FAX

Send replies to: usenet at richseifert dot com

Vote
Twitter Facebook LinkedIn
S

Thanks a lot Rich! That solves the puzzle to me!

Bext regards, Joseph

Vote
Twitter Facebook LinkedIn

Join the Discussion

Have something to add? Share your thoughts — no account required.

Didn't find your answer?

Ask the community — no account required