Hello,=20 I have to detect the Start of a Ethernet Frame. So I want to make use of a = FPGA. The FPGA will be connected to the MII pins of the PHY (TXD 0-3 and RX= D 0-3, the Clocks, TX_EN and RX_DV). What I know from the IEEE802.3 Datashe= ets is that the preamble will be send as 14 Nibbles and after that 2 Nibble= s the SFD. In transmitting case it will be like that:=20 TxD0 X 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Data=20 TxD1 X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Data=20 TxD2 X 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Data=20 TxD3 X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Data=20 TxEn 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1..=20
So I thought that I can trigger the rising edge from TxD3 in the 16. Cylce = or from Tx_En. But if I only check one wire there could be errors right? Ho= w do I check for more than one Cylce? Do I need a State machine? Is this th= e correct path?=20
I found the example of SFD detection from OpenCores.org of the EtherMac pro= ject, but i dont have any verilog or vhdl knowledge. =20 Thatswhy i wanted to use the Xilinx ISE Schematic tool and some fast logic.
So can you help me by giving me some advice how to make use of some fast lo= gic.=20 Do i need some FIFOs oder Latches?=20
Thank you very much and greetings