T1 SSM

Unfortunately, I don't have access to TR-33 and I have some questions about the behavior of the SSM on a T1. I don't quite understand the transmit order. What exactly is an abort sequence in this context?

I'm working on a driver for the DS26504 framer chip. The device documentation seems to indicate that the abort sequence is eight consecutive ones on the FDL. The reason I'm confused is that I see this whenever I'm actually receiving SSM, whereas I would expect not to receive all ones if the SSM was placed there. Is the SSM in the FDL generally followed or preceded by an abort sequence? I don't see the abort sequence if the sender isn't transmitting SSM on that interface. I'm trying not to ask the vendor this question because I'm not sure what the expected behavior is according to the standard.

Also, what would be the significance of receiving 30 FDL bits without receiving an abort sequence? I have looked at the Standards I have access to, such as T1.403, GR-253, GR-378, and G.781. I wasn't able to find this information. Any help would be greatly appreciated.

Thanks,

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dan.mazz
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