8051 memory access hardware question

I have a homebuilt home control system based on an 80c51FA processor. I recently had a memory failure on it. It currently uses 32K x 8 bit mmemories, sharing the space for code and variables. I would like to replace the 2 memories with one

128k x 8 bit memory.

It has been a long time since I did much hardware design. I am trying to figure out how I can connect one 128k byte memory to map to 64 KB of program and 64 KB of data memory, which would mean I need to select half the chip depending on whether I am reading program code or data. Looking at the hardware manual, I don't see an easy way to do this, as it seems that the RD\\ or PSEN\\ are normally used to access data or program memory, and I need a high address bit to differentiate them.

The chip only handles a 64 KB address space. I would jumper the program memory to be data memory while I loaded the program, then switch the jumper back.

Can anyone offer me any suggestions of how to do this? I would really like to increase the available space in both memories. I have one 32 pin memory socket and one 28 pin socket available with a fair amount of flexibility of signals to the high address and chip select bits.

Reply to
Bob F
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How about RD\\ | PSEN\\ -> CS, PSEN\\ -> high address bit?

bill

Reply to
William W Martin

As I see it, that would mean the high address bit would go low as PSEN\\ goes low. Looking at an HM628128LP, I see no spec for Address stable to PSEN\\ (CS) low, so maybe that would work. I could throw in a couple gate delays. for the PSEN\\ compared to the high address bit. Should that work?

Reply to
Bob F

Why not have the code in ROM ? That's the norm.

Graham

Reply to
Eeyore

On Mon, 10 Nov 2008 21:15:43 -0800, "Bob F" put finger to keyboard and composed:

I suspect that you need only look at the problem from the perspective of the RAMs, not the CPU.

I don't remember much about the 8051, but I would think that your two RAMs would have OE*, CS*, and WE* pins.

If the WE* pins are wired together, then wire them to your 128KB RAM.

The other two pins could be wired as follows:

|---- OE1* ----| \\ |\\ | |o---| |o--- OE* OE2* ----| / |/ |---/

|---- CS1* ----| \\ |\\ | |o---| |o--- CS* CS2* ----| / |/ ----/

Address lines A0 and A15 of your 128KB RAM would be wired to your CPU, and A16 could be wired to either CS1* or CS2*.

The inverters could be constructed from the remaining two NAND gates in a quad package.

- Franc Zabkar

Reply to
Franc Zabkar

This unit uses an evauation board monitor program in the 80C51 to load programs into RAM from a computer. I have used it this way for the last 15 or so years with few problems. I have no easy way to burn PROMs. It is nice for quick program modifications.

Reply to
Bob F

As I look at this from the memory point of view, I begin to think it will indeed work. I was worried that the address setup time requirement would prevent it, but that may not be the case.

If anyone has actually done this, I'd love to hear about your success.

Reply to
Bob F

On Wed, 12 Nov 2008 22:44:11 -0800, "Bob F" put finger to keyboard and composed:

I have used a similar technique when repairing a Commodore 5-1/4" floppy disc drive. It had a faulty 2332 (?) ROM, so I replaced all 3 ROMs with a single EPROM and used a scheme such as the above to decode the additional address lines. I had to make an adapter for my device programmer so that it could read a 2332 ROM in a 2732 EPROM socket, and I had to provides jumpers to allow for active low or active high OE and/or CS pins. I removed the 3x 2332 IC sockets and replaced them with a daughter PCB connected to the main PCB via a single wirewrap socket and a few fly wires. IIRC the decoding was done using a single

74LS00 or 74S00 quad NAND. The address setup time may be accounted for by the delays in the two gates.

- Franc Zabkar

Reply to
Franc Zabkar

Sounds good.

Interestingly, I just found somw SRAMs on ebay which seem to use a completely different ordering on the address lines than the convention my sockets are wired to.

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I'm guessing that the difference in the address pin numbering would not keep it from operating properly. Thet each address is distinct, and it would give appropriate data for each access, even if they were not coming out of the memory matrix in order. Does this sound right.

Also, would you expect that using a significantly faster memory would cause any problem. My current memory is 55 nS, I believe, and I found one source for 15 nS chips. My board is a hand-wired device (Wires soldered pin-to-pin.)

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Reply to
Bob F

On Wed, 12 Nov 2008 23:46:42 -0800, "Bob F" put finger to keyboard and composed:

I've seen this difference, too, but, like you, I can't see a problem with it. It may be confusing, though, when trying to read a ROM whose address lines don't match up with convention.

I haven't yet had a problem substituting a faster RAM for a slower one, but I've only tried my hack with ROMs, which are relatively slow devices.

- Franc Zabkar

Reply to
Franc Zabkar

Get a FLASH based 8051 like the 89s52 ?? check their FLASH memory sizes and program it in circuit using the parallel port adaptor lead supplied by Atmel along with their programming tool. It seems a bit flakey at times but does work. If the port pins required conflict with your circuit you only need power xtal and reset to program it.

I actually made my own adaptor from Atmel's app notes not realising Farnell sold them and tagged it onto another PCB.

Graham

Reply to
Eeyore

I doubt an ancient version of the 8051 will reach enough speed to worry about unless you're using those darn new-fangled accelerated ones !

Graham

Reply to
Eeyore

Thanks for the suggestion. This would at least allow me to modify the monitor program within the CPU to be able to program external flash memory.

Reply to
Bob F

Farnell's online search engine refuses to identify the part (which is why I never originally found it), but it wasn't expensive, something like £25 bundled with the software when I found it in the paper catalogue. Atmel's site proves equally unhelpful but I have some files on it here.

Philips (oops NXP) do something similar but unhelpfully different it seems.

If you use ExpressPCB I could send you the design files for it. It's easy to tag it onto another board, you can even make them 'snap apart', and at ~ 4cm sq approx won't cost anything if you have a design going through already. It's all through hole for simple assembly and fits in a typical 25D sub to 25D sub adaptor housing.

Graham

Reply to
Eeyore

That's how Atmel do it too.

The search term was 'AT89ISP'

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The 'technical data sheet' gives partial info but no schematic. But I have that. There have been a couple of revisions to add functionality for newer processors. I think I incorprated those into my last 'spin' of the board. It is all there on the Atmel site but you have to dig deep.

Graham

Reply to
Eeyore

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