I would like to understand in more detail on how often should I transmit Pause frame from the chip I am designing.
The Pause frame timer value inserted in the frame depends on:
- The Buffer on my side is getting almost full
- The Network cable length (round trip delay to the other end)
I need to clarify the following issues:
- I need some equation, that I need to base on, to compute the timer value that Needs to be inserted in the pause frame . I have a programmable pause timer register that is used to get the value to be inserted.
- If my buffer is still almost full even after transmitting the first pause frame, what is the timer value I need to insert in the second Pause frame.
- Second case where my buffer is not full anymore, after transmitting the first pause. But I don't want the other end to wait any more. Should I consider sending another Pause at this time with 0 timer value Or I should have the correct value that should have been sent on the first pause frame.
- Pause frame is 512 bit time means ??? Does it mean Val= Timer Value * 512 and Every time I transfer 8 bits, the "val" should decrement by 8.
Please answer my questions. If you have any papers that describe about Pause frames, Please send me the URL.
thanks, Nikki