CRC
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Posted by Ruddha on March 21, 2007, 4:06 am
Please log in for more thread options Hi, I have written some Verilog code to compute CRC for an ethernet packet. There seem to be two different implementations - one where the initial value is FFFFFFFF and the final bits are complemented before transmission, and another version where the final bits are taken byte wise and reversed before inversion. Which is the correct CRC procedure? Aniruddha | ||||||||||
