JFETs and "pinch-off" - two meanings?
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Posted by billcalley on March 29, 2006, 7:34 pm
Please log in for more thread options Hi All, When reading descriptions on the operation of JFETs, I repeatedly see mention of "pinch-off". Some books on JFETs describe pinch-off as the point that the drain-to-source voltage (Vds) is just high enough so as not to affect the drain current if Vds happens to increase; while other books describe pinch-off as the point that the JFET's gate bias is negative enough to shut down, or "pinch-off", all the drain current. Which is correct? Thanks! -Bill | ||||||||||||||||||||||
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Posted by Tim Wescott on March 29, 2006, 7:50 pm
Please log in for more thread options billcalley wrote: Insisting on one or the other just starts a religious war. I prefer your former definition, but that's because it's what I learned in school. Then again, when I was in school I thought it was misleading... -- Tim Wescott Wescott Design Services http://www.wescottdesign.com Posting from Google? See http://cfaj.freeshell.org/google/ | ||||||||||||||||||||||
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Posted by Joerg on March 29, 2006, 7:52 pm
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Hello Bill, > When reading descriptions on the operation of JFETs, I repeatedly
> see mention of "pinch-off". Some books on JFETs describe pinch-off > as the point that the drain-to-source voltage (Vds) is just high enough > so as not to affect the drain current if Vds happens to increase; while > other books describe pinch-off as the point that the JFET's gate bias > is negative enough to shut down, or "pinch-off", all the drain > current. Which is correct? > The latter, sez Winfield Hill in "The Art of Electronics". And he ought to know :-) Regards, Joerg http://www.analogconsultants.com | ||||||||||||||||||||||
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Posted by Winfield Hill on March 29, 2006, 9:55 pm
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Joerg wrote... >
>> When reading descriptions on the operation of JFETs, I repeatedly
>> see mention of "pinch-off". Some books on JFETs describe pinch-off >> as the point that the drain-to-source voltage (Vds) is just high enough >> so as not to affect the drain current if Vds happens to increase; while >> other books describe pinch-off as the point that the JFET's gate bias >> is negative enough to shut down, or "pinch-off", all the drain >> current. Which is correct? >
> The latter, sez Winfield Hill in "The Art of Electronics". And he > ought to know :-) Did I say that? Pinch off is a gate-voltage definition. It's one of two things: the gate voltage the manufacturer specifies, e.g. Vgs(off) at Id = 1nA, 10nA, 10uA, 250uA, etc., or better, the gate voltage Vth where the extrapolated sqrt Id vs Vgs plot goes through zero (AoE figure 3.13, page 122). While you won't get the latter parameter from a datasheet, any JFET will beautifully provide the data for a textbook extrapolated sqrt-Id plot. Sadly the data from next JFET in the batch likely won't very closely match that plot; the rule will be the same but its extrapolated Vth voltage will be different. -- Thanks, - Win | ||||||||||||||||||||||
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Posted by Joerg on March 30, 2006, 1:07 pm
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Hello Win, >>> When reading descriptions on the operation of JFETs, I repeatedly
>>>see mention of "pinch-off". Some books on JFETs describe pinch-off >>>as the point that the drain-to-source voltage (Vds) is just high enough >>>so as not to affect the drain current if Vds happens to increase; while >>>other books describe pinch-off as the point that the JFET's gate bias >>>is negative enough to shut down, or "pinch-off", all the drain >>>current. Which is correct? >>
>>The latter, sez Winfield Hill in "The Art of Electronics". And he >>ought to know :-) >
> Did I say that? Pinch off is a gate-voltage definition. It's one > of two things: the gate voltage the manufacturer specifies, e.g. > Vgs(off) at Id = 1nA, 10nA, 10uA, 250uA, etc., or better, the gate > voltage Vth where the extrapolated sqrt Id vs Vgs plot goes through > zero (AoE figure 3.13, page 122). While you won't get the latter > parameter from a datasheet, any JFET will beautifully provide the > data for a textbook extrapolated sqrt-Id plot. Sadly the data from > next JFET in the batch likely won't very closely match that plot; > the rule will be the same but its extrapolated Vth voltage will be > different. > I believe you did, AoE page 120, the paragraph under figure 3.11. "For JFETs the gate-source voltage at which drain current approaches zero is called...". But I agree, what is considered close enough to zero varies from mfg to mfg and might even be influenced by their marketeers. I wish there was some kind of standard, like x many dB under abs max current or something. Then again, as you said, the lot variations are so huge that it wouldn't make much sense to nail V pinch-off down to within a few hundred mV. Regards, Joerg http://www.analogconsultants.com | ||||||||||||||||||||||
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>
> When reading descriptions on the operation of JFETs, I repeatedly
> see mention of "pinch-off". Some books on JFETs describe pinch-off
> as the point that the drain-to-source voltage (Vds) is just high enough
> so as not to affect the drain current if Vds happens to increase; while
> other books describe pinch-off as the point that the JFET's gate bias
> is negative enough to shut down, or "pinch-off", all the drain
> current. Which is correct?
>
> Thanks!
>
> -Bill
>