FET basics
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Posted by vic on January 24, 2007, 1:49 pm
Please log in for more thread options I'm studying the input stage of the following frequency meter : http://www.madlab.org/kits/FrequencyMeter.pdf http://www.madlab.org/kits/frqmeter.html I'm having a little trouble understanding how the FET works. First, the polarization of the transistor. To operate, Vg must be lower than Vs. Let's say there is no input signal so Vg = 5*2.2k/12.2k = 0.9V. TR3 is wired as constant current source, so Ids is fixed = 1mA. There is also 1mA through R1, so Vd = 5-1k*1mA = 4V. From there, I don't see how it can be sure that Vs > Vg. Vds seems
indeterminate at this point. Is he just assuming that Vds always is
lower than 3.1V ? Second, various online lessons I've found about FETs say that Ids is a function of Vgs. Here Ids is fixed by TR3, so what is varying ? Thanks for taking time to read this, vic | ||||||||||||||||||||||
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Posted by John Popelish on January 24, 2007, 6:47 pm
Please log in for more thread options > Hi,
> > I'm studying the input stage of the following frequency meter : > http://www.madlab.org/kits/FrequencyMeter.pdf > http://www.madlab.org/kits/frqmeter.html > > I'm having a little trouble understanding how the FET works. > > First, the polarization of the transistor. > To operate, Vg must be lower than Vs. Yes, more negative. Junction fets are normally on devices that turn off as the gate side of the gate to channel junction becomes more reverse biased. > Let's say there is no input signal so Vg = 5*2.2k/12.2k = 0.9V.
(neglecting any base current to TR3) > TR3 is wired as constant current source, so Ids is fixed = 1mA.
Yes, though the current is not so clearly 1 mA. If the base to emitter drop is about .6 volts, then there is .3 volts left across the 220 ohm emitter resistor, for a current of about 1.4 mA. But the exact value is not so important to the concept. > There is also 1mA through R1, so Vd = 5-1k*1mA = 4V.
> From there, I don't see how it can be sure that Vs > Vg. Vds seems > indeterminate at this point. The source voltage will be pulled down by TR3 until it is just far enough more positive than the gate voltage, to allow TR1 to carry the 1mA. If the source voltage were more positive than that required amount, there would not be a mA passing through the 220 ohm emitter resistor, so the base current for TR3 would increase, and the collector voltage would be pulled down to a less positive voltage, turning TR1 on more. If the source voltage of TR1 were less positive than what would regulate the drain current to 1 mA, there would be more current passing through the 220 ohm emitter resistor and the base current to TR1 would decrease, causing its collector voltage to go more positive. So the circuit finds whatever positive (with respect to the gate) source voltage it takes to force TR1 to carry all the current passing through TR3. To calculate what voltage is, you would need a set of curves that show the drain current for many combinations of drain to source voltage at various gate to source voltages. > Is he just assuming that Vds always is
> lower than 3.1V ? Assuming it is possible for the fet to carry the regulated current, the source voltage must fall somewhere between .9 and 3.1 volts. > Second, various online lessons I've found about FETs say that Ids is a
> function of Vgs. Here Ids is fixed by TR3, so what is varying ? In this case, the average current is regulated by TR3, while variations around that average are controlled by TR1. | ||||||||||||||||||||||
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Posted by vic on January 25, 2007, 6:43 am
Please log in for more thread options John Popelish wrote:
>> Second, various online lessons I've found about FETs say that Ids is a
>> function of Vgs. Here Ids is fixed by TR3, so what is varying ? >
> In this case, the average current is regulated by TR3, while variations > around that average are controlled by TR1. OK, so the variations of Vs are applied on capacitor C5, which causes a current proportional to it's capacity, and this current in turn causes the voltage across R1 to vary. Is this correct ? Thanks all, I think I understand better now :) | ||||||||||||||||||||||
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Posted by Andrew Holme on January 25, 2007, 10:15 am
Please log in for more thread options
> John Popelish wrote:
> >> Second, various online lessons I've found about FETs say that Ids is a
> >> function of Vgs. Here Ids is fixed by TR3, so what is varying ? >
> > In this case, the average current is regulated by TR3, while variations
applied on capacitor C5, which causes a
> > around that average are controlled by TR1.OK, so the variations of Vs are > current proportional to it's capacity, and this current in turn causes
> the voltage across R1 to vary. Is this correct ? > It helps to think about AC (signal) and DC (average / bias) conditions seperately. Capacitors are effectively open-circuit to DC, and low-impedance to AC. Think of the signal as a small AC component superimposed on top of the steady-state DC average. If it were not for C5, Vgs and Id would be constant, and the input signal would appear on Vs. The amount of charge stored on C5 is related to the voltage across it by: Q = CV To change this voltage, you have to move charge. Current is the rate of change of charge: I = dQ/dt You need a big current for a short time, or a small current for a long time. At signal freqeuncies, we do not have a long time, and the voltage cannot change fast enough in response to cycles of input freqeuncy, so C5 keeps Vs fairly constant. This means the AC input signal appears across Vgs, and this forces Id to vary in sympathy. | ||||||||||||||||||||||
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Posted by John Popelish on January 25, 2007, 10:54 am
Please log in for more thread options vic wrote:
> John Popelish wrote:
>>> Second, various online lessons I've found about FETs say that Ids is
>>> a function of Vgs. Here Ids is fixed by TR3, so what is varying ? >>
>> In this case, the average current is regulated by TR3, while >> variations around that average are controlled by TR1. >
> OK, so the variations of Vs Make that the variations of Is... > are applied on capacitor C5, which causes a
> current proportional to it's capacity, which cause very small voltage changes, inverse to its capacity (I=C*(dv/dt) so dv or change in voltage = dt*I/C or time * current / capacitance) across the capacitor > and this current in turn causes
> the voltage across R1 to vary. Is this correct ? > > Thanks all, I think I understand better now :) If the capacitor is large enough, it will look like a voltage supply at signal frequencies. In other words, the signal current, during a half cycle of the signal, will pass current through the capacitor without changing its voltage significantly. The next half cycle will pass the same current in the opposite direction, again not changing the voltage, significantly. And since AC averages zero DC current, those alternating insignificant changes will not add up to any net, long term change of capacitor voltage. During this signal current detour through the capacitor, TR3 holds to a steady current that is the average current through TR1. The capacitor voltage it is initially defined by the DC bias point that TR3 and TR1 settle to. So, for signal analysis, just replace TR3 and the capacitor with a battery that has the DC voltage you measure (or calculate) at the source of TR1. | ||||||||||||||||||||||
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