Electronics Design PLL frequency multiplier.

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Subject Author Date
PLL frequency multiplier. Mike 07-03-08
Posted by Mike on July 3, 2008, 3:07 pm
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I need a circuit that takes a 400hz sync pulse and multiplies it to
19.2khz.

I was reading around the net on PLL multipliers, but everything I have
seen are way up into the mhz range with really no schematics on aiding
to design one.

any ideas? thanks.

Posted by Frank Buss on July 3, 2008, 3:16 pm
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Mike wrote:

> I need a circuit that takes a 400hz sync pulse and multiplies it to
> 19.2khz.
>
> I was reading around the net on PLL multipliers, but everything I have
> seen are way up into the mhz range with really no schematics on aiding
> to design one.

I've never used it, but maybe the old 4046 works:

http://www.fairchildsemi.com/ds/MM/MM74HC4046.pdf

--
Frank Buss, fb@frank-buss.de
http://www.frank-buss.de, http://www.it4-systems.de

Posted by Joerg on July 3, 2008, 4:13 pm
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Frank Buss wrote:
> Mike wrote:
>
>> I need a circuit that takes a 400hz sync pulse and multiplies it to
>> 19.2khz.
>>
>> I was reading around the net on PLL multipliers, but everything I have
>> seen are way up into the mhz range with really no schematics on aiding
>> to design one.
>
> I've never used it, but maybe the old 4046 works:
>
> http://www.fairchildsemi.com/ds/MM/MM74HC4046.pdf
>

But the real Frank Buss method would be to pipe that 400Hz into a uC and
run a timer in there. A software loop would keep adjusting the timer's
overflow register until the timer does exactly 96 rollovers per 400Hz
cycle. Then use that timer overflow signal to toggle a port pin which
will now deliver exactly 19.2kHz at 50% duty cycle. This method should
require the least in parts. Heck, the uC doesn't even need a stable
clock, it can run off its on-chip RC oscillator. Best case it'll be two
components, the uC itself and a 0.1uF bypass cap.

Of course us analog guys will always have run out of timers by the time
a function such as this is added into the mix. Somehow there are never
enough timers ...

Mike, I can't see your posts because you probably use the google domain.
But if you want to build something around a 4046 here is the recipe,
figure 2:

http://www.mlecmn.net/~lyle/pc-syn/pc-syn.htm

The divider would be a bit more cumbersome because you have to provide a
divide ration of 48 in this circuit. Most likely needs two chips instead
of that one. But I am sure you can piece that together. Your 400Hz goes
into pin 14 and your 19.2kHz emerge at pin 4. The timing parts to the
right of the 4046 may also need some changes, that's where the datasheet
comes in.

If this runs at voltages <5V I suggest to use 74HC series chips. The PLL
comes in that family as well, would be called 74HC4046.

--
Regards, Joerg

http://www.analogconsultants.com/

"gmail" domain blocked because of excessive spam.
Use another domain or send PM.

Posted by Frank Buss on July 3, 2008, 4:32 pm
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Joerg wrote:

> But the real Frank Buss method would be to pipe that 400Hz into a uC and
> run a timer in there. A software loop would keep adjusting the timer's
> overflow register until the timer does exactly 96 rollovers per 400Hz
> cycle. Then use that timer overflow signal to toggle a port pin which
> will now deliver exactly 19.2kHz at 50% duty cycle. This method should
> require the least in parts. Heck, the uC doesn't even need a stable
> clock, it can run off its on-chip RC oscillator. Best case it'll be two
> components, the uC itself and a 0.1uF bypass cap.

It depends on the accuracy requirements. If I use a cheap PIC with 4 MHz
internal clock, I would need some machine cycles (4 MHz PICs runs with one
million instructions per second) to toggle the pin. Would need considerably
work to balance the code paths for the same time and even then there would
be a jitter of about 2% (19.2 kHz / 1 MHz * 100), and worse when I need to
adjust it up/down by one. I assume the CD4046 is more accurate.

--
Frank Buss, fb@frank-buss.de
http://www.frank-buss.de, http://www.it4-systems.de

Posted by Joerg on July 3, 2008, 7:37 pm
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Frank Buss wrote:
> Joerg wrote:
>
>> But the real Frank Buss method would be to pipe that 400Hz into a uC and
>> run a timer in there. A software loop would keep adjusting the timer's
>> overflow register until the timer does exactly 96 rollovers per 400Hz
>> cycle. Then use that timer overflow signal to toggle a port pin which
>> will now deliver exactly 19.2kHz at 50% duty cycle. This method should
>> require the least in parts. Heck, the uC doesn't even need a stable
>> clock, it can run off its on-chip RC oscillator. Best case it'll be two
>> components, the uC itself and a 0.1uF bypass cap.
>
> It depends on the accuracy requirements. If I use a cheap PIC with 4 MHz
> internal clock, I would need some machine cycles (4 MHz PICs runs with one
> million instructions per second) to toggle the pin. Would need considerably
> work to balance the code paths for the same time and even then there would
> be a jitter of about 2% (19.2 kHz / 1 MHz * 100), and worse when I need to
> adjust it up/down by one. I assume the CD4046 is more accurate.
>

Another thought in case this comes up in some project: If you make sure
the timer overflow has the highest interrupt priority there won't be
more jitter than the granularity of the master clock. Just make sure the
assembler routine for that ISR takes exactly xx clock cycles every time.

--
Regards, Joerg

http://www.analogconsultants.com/

"gmail" domain blocked because of excessive spam.
Use another domain or send PM.

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