Clocks and baluns
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Posted by Prune on January 31, 2008, 7:36 pm
Please log in for more thread options I intend to use AD9510 for clock distribution, as it has fery low additive phase noise. My problem is, according to the datasheet performance is degraded if input exceeds 2 V peak-to-peak, and the low jitter TCXO I am considering has the typical either 3.3 V or 5 V output. Someone suggested I use a 2:1 or 3:1 balun, but I'm concerned about bandwidth, since the clock is square wave output (because the AD9510 datasheet says it needs high slew rate on the inputs for optimal performance). I'm also not sure how to handle transmission line effects. With a PCB track impedance is easy to control, and I normally use series termination resistors at the source on high speed lines to get a decent waveform, but I'm not sure what inserting a balun will do, how to choose the balun, and where to locate it for best performance (at the clock or at the distribution IC's input). The TCXO I'm using has about -110 dB phase noise at 10 Hz offset from the fundamental of 24 MHz, and I'd like to not get more than 5 dB increase from the overall distribution circuit--transformer+AD9510. What's the best approach? | ||||||||||||||||||||||
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Posted by Joerg on January 31, 2008, 7:58 pm
Please log in for more thread options Why not just use a (symmetrical) resistive divider? -- Regards, Joerg http://www.analogconsultants.com/ | ||||||||||||||||||||||
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Posted by Prune on January 31, 2008, 8:18 pm
Please log in for more thread options Hi, thanks for the fast reply.
I was concerned about input capacitance of the IC making a lowpass with added resistance and limiting slew rate, though it looks like it's only 2 pF... The clock is specified for HCMOS output, 15 pF and <5 ns risetime. Not sure how performance of the clock's output stage would be affected by a non-standard load. If I do use a resistive divider, would it be best to put the clock right next to the IC with minimum PCB track in between, just the divider? > Prune wrote:
>> Question for the RF-knowledgeable:
>> I intend to use AD9510 for clock distribution, as it has fery low >> additive phase noise. My problem is, according to the datasheet >> performance is degraded if input exceeds 2 V peak-to-peak, and the >> low jitter TCXO I am considering has the typical either 3.3 V or 5 V >> output. Someone suggested I use a 2:1 or 3:1 balun, but I'm >> concerned about bandwidth, since the clock is square wave output >> (because the AD9510 datasheet says it needs high slew rate on the >> inputs for optimal performance). I'm also not sure how to handle >> transmission line effects. With a PCB track impedance is easy to >> control, and I normally use series termination resistors at the >> source on high speed lines to get a decent waveform, but I'm not sure >> what inserting a balun will do, how to choose the balun, and where to >> locate it for best performance (at the clock or at the distribution >> IC's input). The TCXO I'm using has about -110 dB phase noise at 10 >> Hz offset from the fundamental of 24 MHz, and I'd like to not get >> more than 5 dB increase from the overall distribution >> circuit--transformer+AD9510. What's the best approach? >
> > Why not just use a (symmetrical) resistive divider? > | ||||||||||||||||||||||
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Posted by Joerg on January 31, 2008, 8:28 pm
Please log in for more thread options Prune wrote:
> Hi, thanks for the fast reply.
> I was concerned about input capacitance of the IC making a lowpass with > added resistance and limiting slew rate, though it looks like it's only 2 > pF... The clock is specified for HCMOS output, 15 pF and <5 ns risetime. > Not sure how performance of the clock's output stage would be affected by a > non-standard load. > If I do use a resistive divider, would it be best to put the clock right > next to the IC with minimum PCB track in between, just the divider? > Please post underneath the previous text, makes it easier for others to follow (and respond). It doesn't really matter but if you place it far away you must calculate the resulting input impedance and size the traces accordingly. IOW so they have the correct characteristic impedance. It is generally best to place RF stuff close together in order to minimize EMI. >
> >> Prune wrote:
>>> Question for the RF-knowledgeable:
>>> I intend to use AD9510 for clock distribution, as it has fery low >>> additive phase noise. My problem is, according to the datasheet >>> performance is degraded if input exceeds 2 V peak-to-peak, and the >>> low jitter TCXO I am considering has the typical either 3.3 V or 5 V >>> output. Someone suggested I use a 2:1 or 3:1 balun, but I'm >>> concerned about bandwidth, since the clock is square wave output >>> (because the AD9510 datasheet says it needs high slew rate on the >>> inputs for optimal performance). I'm also not sure how to handle >>> transmission line effects. With a PCB track impedance is easy to >>> control, and I normally use series termination resistors at the >>> source on high speed lines to get a decent waveform, but I'm not sure >>> what inserting a balun will do, how to choose the balun, and where to >>> locate it for best performance (at the clock or at the distribution >>> IC's input). The TCXO I'm using has about -110 dB phase noise at 10 >>> Hz offset from the fundamental of 24 MHz, and I'd like to not get >>> more than 5 dB increase from the overall distribution >>> circuit--transformer+AD9510. What's the best approach? >>
>> Why not just use a (symmetrical) resistive divider? >> >
-- Regards, Joerg http://www.analogconsultants.com/ | ||||||||||||||||||||||
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Posted by John Larkin on January 31, 2008, 8:57 pm
Please log in for more thread options wrote:
>Question for the RF-knowledgeable:
>I intend to use AD9510 for clock distribution, as it has fery low additive >phase noise. My problem is, according to the datasheet performance is >degraded if input exceeds 2 V peak-to-peak, and the low jitter TCXO I am >considering has the typical either 3.3 V or 5 V output. Someone suggested >I use a 2:1 or 3:1 balun, but I'm concerned about bandwidth, since the >clock is square wave output (because the AD9510 datasheet says it needs >high slew rate on the inputs for optimal performance). I'm also not sure >how to handle transmission line effects. With a PCB track impedance is >easy to control, and I normally use series termination resistors at the >source on high speed lines to get a decent waveform, but I'm not sure what >inserting a balun will do, how to choose the balun, and where to locate it >for best performance (at the clock or at the distribution IC's input). The >TCXO I'm using has about -110 dB phase noise at 10 Hz offset from the >fundamental of 24 MHz, and I'd like to not get more than 5 dB increase from >the overall distribution circuit--transformer+AD9510. What's the best >approach? Good grief, a 60 page datasheet for a clock buffer! What I'd do is long run? osc--R1---------------------------+---C1-----CLK1 | | +--CLK1b | | R2 C2 | | | | | | gnd gnd where the impedance of [long run] = R2. Tweak R1 for desired signal swing into the adi chip. John | ||||||||||||||||||||||
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> I intend to use AD9510 for clock distribution, as it has fery low additive
> phase noise. My problem is, according to the datasheet performance is
> degraded if input exceeds 2 V peak-to-peak, and the low jitter TCXO I am
> considering has the typical either 3.3 V or 5 V output. Someone suggested
> I use a 2:1 or 3:1 balun, but I'm concerned about bandwidth, since the
> clock is square wave output (because the AD9510 datasheet says it needs
> high slew rate on the inputs for optimal performance). I'm also not sure
> how to handle transmission line effects. With a PCB track impedance is
> easy to control, and I normally use series termination resistors at the
> source on high speed lines to get a decent waveform, but I'm not sure what
> inserting a balun will do, how to choose the balun, and where to locate it
> for best performance (at the clock or at the distribution IC's input). The
> TCXO I'm using has about -110 dB phase noise at 10 Hz offset from the
> fundamental of 24 MHz, and I'd like to not get more than 5 dB increase from
> the overall distribution circuit--transformer+AD9510. What's the best
> approach?