CPLD Jitter
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Posted by Andrew Holme on August 28, 2005, 5:44 pm
Please log in for more thread options The dividers and the phase detector of my experimental frequency synthesizer are implemented in a 15ns Altera MAX7000S CPLD. I've tried different multiplication factors (kN) to see how the close-in phase noise varies. At a 1 KHz offset, I get: -82 dBc/Hz for N=198 (VCO=19.8 MHz, comparison freq = 100 KHz) -95 dBc/Hz for N=39 (VCO=19.5 MHz, comparison freq = 500 KHz) Calculating the equivalent phase noise at the PFD: -82-20*log10(198) = -128 dBc/Hz -95-20*log10(39) = -127 dBc/Hz Given the 5:1 ratio of comparison frequencies, at a guess, I'd expect these to differ by 13 dB if the noise was mainly due to a fixed amount of time jitter at the PFD. I'm using a 10 MHz canned crystal oscillator, which I'm dividing down (inside the CPLD) to obtain the reference frequencies. I've read these are good for at least -130 dBc/Hz (before dividing down) so I'm a bit dissappointed with my noise levels. Maybe it got a bit too hot when I soldered it to the ground plane! I must try another.... Googling for "altera cpld jitter" doesn't turn-up much, and they don't mention jitter in the datasheet. Does anyone know what sort of performance can be expected from a CPLD in this regard? I don't know if the CPLD, or my circuit lash-up is the root cause. A full write-up of the project can be found at http://www.holmea.demon.co.uk/Frac2/Main.htm It has a fractional-N capability, but noise-levels are the same in integer-N mode with the external RAM disabled. Thanks, Andrew. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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Posted by Daniel Lang on August 28, 2005, 2:07 pm
Please log in for more thread options I would suggest inserting a 100 ohm resistor between C3 and C7 and placing a 100uF capacitor in parallel with C7. The noise on the output of U4 is just as critical as the noise on the + input of U3. You may also want to add an RC filter on the output of U5 before feeding it to U6. Daniel Lang | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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Posted by Hal Murray on August 28, 2005, 3:47 pm
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>I'm using a 10 MHz canned crystal oscillator, which I'm dividing down
>(inside the CPLD) to obtain the reference frequencies. I've read these are >good for at least -130 dBc/Hz (before dividing down) so I'm a bit >dissappointed with my noise levels. Maybe it got a bit too hot when I >soldered it to the ground plane! I must try another.... Can you measure the raw oscillator output? It may not be as good as you expect. Many low volume oscillators now use a PLL. They program the dividers rather than grind the crystal to get custom frequencies. I'd expect that numbers like 10 MHz would have enough volume so that they would avoid the PLL but maybe it's cheaper to have one production setup and use it for the common frequencies too. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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Posted by Ken Smith on August 28, 2005, 5:30 pm
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[...] >Googling for "altera cpld jitter" doesn't turn-up much, and they don't
>mention jitter in the datasheet. Does anyone know what sort of performance >can be expected from a CPLD in this regard? I don't know if the CPLD, or my >circuit lash-up is the root cause. If you have other signals running through the CPLD, part of the problem could be crosstalk. Power supply noise will also show up as a jitter. There seems to be a bad solder joint in the upper left corner. Check the LM78M05 for oscillations. We don't see the traces hooking up the bypasses on it. You also have to be careful when making things like flip-flop phase comparitors inside the MAX series. When I made one, I had to add some extra logic after the flip-flops so that the "both" state of the flip-flop pair was used to gate off the output. I think the CLRN timing was the problem bit once I got it working, I stopped looking for the root cause. IIRC: BothLatch = (UpFlipFlop # DownFlipFlop) & BothLatch # UpFlipFlop & DownFlipFlop; Up = UpFlipFlop & !DownFlipFlop & !BothLatch; >
>A full write-up of the project can be found at >http://www.holmea.demon.co.uk/Frac2/Main.htm It has a fractional-N >capability, but noise-levels are the same in integer-N mode with the >external RAM disabled. > >Thanks, >Andrew. > > -- -- kensmith@rahul.net forging knowledge | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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Posted by Brian Davis on August 28, 2005, 7:32 pm
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Andrew, >
Asides from the supply/clocking suggestions already made,
> Does anyone know what sort of performance can be expected > from a CPLD in this regard? > I'd also add the following caution: the output stages of most programmable digital parts are not intended for producing clean reference signals to a PLL used for low-noise RF signal generation. A few times over the years that I've considered doing this, the first thing I've done is build something like a pulse output divide-by-ten in the intended technology, driven the part with an oscillator having known phase noise, and looked at the divider output on both a spectrum analyzer & phase noise measurement system. Most of the programmable parts I've measured have had output spurs 50-60 db down that vary strongly in frequency with supply voltage, and can cross over the intended output frequency, making it impossible to keep them out of the loop BW. ( also, the crud in the output spectrum will generally behave differently with an even duty cycle output than for a pulse output divider ) other (hastily conceived) random thoughts: - what's the noise floor of your spectrum analyzer at 1 KHz? - try using a surplus ocxo for your 10 MHz source - if you disable the uC/SRAM, and implement a fixed divide entirely internal to the CPLD, does the noise get any better? have fun, Brian | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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> synthesizer
> are implemented in a 15ns Altera MAX7000S CPLD. I've tried different
> multiplication factors (kN) to see how the close-in phase noise varies.
> At
> a 1 KHz offset, I get:
>
> -82 dBc/Hz for N=198 (VCO=19.8 MHz, comparison freq = 100 KHz)
> -95 dBc/Hz for N=39 (VCO=19.5 MHz, comparison freq = 500 KHz)
>
> Calculating the equivalent phase noise at the PFD:
>
> -82-20*log10(198) = -128 dBc/Hz
> -95-20*log10(39) = -127 dBc/Hz
>
> Given the 5:1 ratio of comparison frequencies, at a guess, I'd expect
> these
> to differ by 13 dB if the noise was mainly due to a fixed amount of time
> jitter at the PFD.
>
> I'm using a 10 MHz canned crystal oscillator, which I'm dividing down
> (inside the CPLD) to obtain the reference frequencies. I've read these
> are
> good for at least -130 dBc/Hz (before dividing down) so I'm a bit
> dissappointed with my noise levels. Maybe it got a bit too hot when I
> soldered it to the ground plane! I must try another....
>
> Googling for "altera cpld jitter" doesn't turn-up much, and they don't
> mention jitter in the datasheet. Does anyone know what sort of
> performance
> can be expected from a CPLD in this regard? I don't know if the CPLD, or
> my
> circuit lash-up is the root cause.
>
> A full write-up of the project can be found at
> http://www.holmea.demon.co.uk/Frac2/Main.htm It has a fractional-N
> capability, but noise-levels are the same in integer-N mode with the
> external RAM disabled.
>
> Thanks,
> Andrew.
>
>