electrical level conversion
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Posted by Kurt Kaiser on December 13, 2006, 5:19 am
Please log in for more thread options Hi there, I'm currently having a serious problem: I got an LVPECL clock synthesizer and I want to connect it to several clock inputs on my FPGA. The FPGA features 2 LVDS interfaces, whereas each LVDS pair is located at opposite sides of the device, meaning there will be some extensive routing to do. I designed a resistor network for the level conversion from LVPECL to LVDS. What I'd like to know now is a) Can I route the 2x2 lines (two times differential to the two opposite sides of the FPGA) one-to-one out of my clock device to the inputs or should I use a dedicated buffer / repeater IC for clock distribution? b) If clock buffer are needed, should I use LVPECL buffers and do the conversion to LVDS level afterwards or should I perfom the conversion before the buffer and then use an LVDS IC? c) Where should I place the level conversion network? Is is better to place it right at the LVPECL output or is it more advisable to do it right before the FPGA inputs after a transmission line length of about 7 cm? Any help, comments, advice is highly appreciated! Thank you all very much. Kurt | ||||
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Posted by John Larkin on December 13, 2006, 9:58 am
Please log in for more thread options On Wed, 13 Dec 2006 11:19:14 +0100, "Kurt Kaiser" Do you need level conversion at all? Some FPGA lvds inputs will work fine with lvpecl drive. But why does the fpga need two identical clocks? What kind of fpga are you using? I sure hope you're not doing a single synchronous logic system driven by two clock inputs! John | ||||
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Posted by Kurt Kaiser on December 13, 2006, 10:10 am
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> But why does the fpga need two identical clocks? What kind of fpga are
> you using? I sure hope you're not doing a single synchronous logic > system driven by two clock inputs! I'm using Virtex-4 FX60. Depending on the implemented designs I will use either the clock input on one side or the other, not both the at the same time of course. So I'm hoping for more flexibility and freedom of clock routing if I have two clocks available and stick to the one that fits better from design to design. The FPGA's input is LVDS. Bye Kurt | ||||
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Posted by John Larkin on December 13, 2006, 11:27 am
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On Wed, 13 Dec 2006 16:10:30 +0100, "Kurt Kaiser" >
>> But why does the fpga need two identical clocks? What kind of fpga are
>> you using? I sure hope you're not doing a single synchronous logic >> system driven by two clock inputs! >
>I'm using Virtex-4 FX60. Depending on the implemented designs I will use >either the clock input on one side or the other, not both the at the same >time of course. So I'm hoping for more flexibility and freedom of clock >routing if I have two clocks available and stick to the one that fits better >from design to design. The FPGA's input is LVDS. > >Bye > >Kurt > OK, <-----fpga----->
pecl+ ----r1-------------------0----------------0----+---r3------ gnd | r2 | pecl- ----r1-------------------0----------------0----+---r3------ gnd something like that maybe. The r1's are very close to the pecl source, and the terminators are fairly close to the fpga's second clock pair. The differential impedance of the traces should slam into a matching termination, r2 || 2*r3. Check the common-mode range of the fpga lvds receivers. It shouldn't take much voltage shifting to get the lvpecl into the legal lvds range. On a Spartan3, I don't think it would take any at all. What sort of Vccio range do these V4's use? They keep going down. One of my guys spent a lot of time - too much time - trying to reduce jitter on a signal that passes through a S3 chip a few times. He did all sorts of exotic stuff to the off-chip circuits, oscillators comparators and such. I finally took a look at it yesterday. Turns out there's an ldo furnishing the 1.2 volt core voltage, and it had a 22 uF ceramic cap across its output, and it was oscillating, a nice 100 mV sawtooth at 24 KHz. That was of course modulating the prop delay of the fpga! Looks like I'm going to break one of my rules and replace the 1206 ceramic cap with a tantalum. John | ||||
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Posted by PeteS on December 13, 2006, 2:24 pm
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John Larkin wrote: > On Wed, 13 Dec 2006 16:10:30 +0100, "Kurt Kaiser"
> >>> But why does the fpga need two identical clocks? What kind of fpga are
>>> you using? I sure hope you're not doing a single synchronous logic >>> system driven by two clock inputs! >> I'm using Virtex-4 FX60. Depending on the implemented designs I will use
>> either the clock input on one side or the other, not both the at the same >> time of course. So I'm hoping for more flexibility and freedom of clock >> routing if I have two clocks available and stick to the one that fits better >>from design to design. The FPGA's input is LVDS. >> Bye >> >> Kurt >> >
Ok if there is no stub to clock destination 1, otherwise I would split:
> OK, > > > <-----fpga-----> > > pecl+ ----r1-------------------0----------------0----+---r3------ gnd > | > r2 > | > pecl- ----r1-------------------0----------------0----+---r3------ gnd > > pecl+ ------r1----------------------------------------0---r3-------- gnd | CK1 r2 pecl- ------r1---------|------------------------------0---r3--------gnd | |------------------------------0---r3--------gnd | CK2 r2 |----------------------------------0--r3--------gnd for a fully terminated solution. Depends on layout, clock speed, allowable mismatch, over/undershoot etc. John's would probably work; I'd only use this where really really necessary. > something like that maybe. The r1's are very close to the pecl source,
> and the terminators are fairly close to the fpga's second clock pair. > The differential impedance of the traces should slam into a matching > termination, r2 || 2*r3. > > Check the common-mode range of the fpga lvds receivers. It shouldn't > take much voltage shifting to get the lvpecl into the legal lvds > range. On a Spartan3, I don't think it would take any at all. For LVDS on Spartan (and V4 I believe), the user provides Vref, so it's just a matter of providing the appropriate Vref, AFAICT. >
> What sort of Vccio range do these V4's use? They keep going down. > > One of my guys spent a lot of time - too much time - trying to reduce > jitter on a signal that passes through a S3 chip a few times. He did > all sorts of exotic stuff to the off-chip circuits, oscillators > comparators and such. I finally took a look at it yesterday. Turns out > there's an ldo furnishing the 1.2 volt core voltage, and it had a 22 > uF ceramic cap across its output, and it was oscillating, a nice 100 > mV sawtooth at 24 KHz. That was of course modulating the prop delay of > the fpga! >
> Looks like I'm going to break one of my rules and replace the 1206 > ceramic cap with a tantalum. > > John I have an LDO that requires an output resistance of no less than 0.5 ohm, (0.5 - 5 ohm is stated, IIRC), so rather than use a tant, I use a ceramic with a 0.5 ohm in series with it - that way at least I don't have to deal with the issues of tants, and the effective ESR maintains over temp a whole lot better than a tant. Cheers PeteS >
> | ||||
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>
>I'm currently having a serious problem: I got an LVPECL clock synthesizer
>and I want to connect it to several clock inputs on my FPGA. The FPGA
>features 2 LVDS interfaces, whereas each LVDS pair is located at opposite
>sides of the device, meaning there will be some extensive routing to do. I
>designed a resistor network for the level conversion from LVPECL to LVDS.
>What I'd like to know now is
>a) Can I route the 2x2 lines (two times differential to the two opposite
>sides of the FPGA) one-to-one out of my clock device to the inputs or should
>I use a dedicated buffer / repeater IC for clock distribution?
>b) If clock buffer are needed, should I use LVPECL buffers and do the
>conversion to LVDS level afterwards or should I perfom the conversion before
>the buffer and then use an LVDS IC?
>c) Where should I place the level conversion network? Is is better to place
>it right at the LVPECL output or is it more advisable to do it right before
>the FPGA inputs after a transmission line length of about 7 cm?
>Any help, comments, advice is highly appreciated!
>
>Thank you all very much.
>Kurt
>