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Posted by Elmo Fuchs on October 30, 2006, 8:28 am
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Hi,
I'm currently developing a PCB featuring a Xilinx Virtex-4 device. Unlinke
the Virtex-II series they now offer the possibility to route various clock
signals to several domains on the FPGA and select them locally by specific
clock multiplexer inputs.
Because of the restricted amount of available pins on the device I selected
(Virtex-4 FX40 with 352 user I/Os) I would like to use just one clock input
on each side of the FPGA, thereby saving clock multiplexer inputs which I
can use as normal GPIOs, and use an external clock multiplexer instead for
my 3 clocks.
Has anyone made experience with such or similar solution? Has anyone used an
external clock multiplexer device for frequencies up to 500 MHz, yet? Is
there any recommendation which chip I could use for this application in
terms of jitter, etc.? And by the way... is my approach advisable, at all?
Any comments are appreciated.
Regards Elmo
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Posted by Andy on October 30, 2006, 2:51 pm
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If you're doing this because you don't have another two available pins
on the FPGA, you need a bigger FPGA, or save pins somewhere else. I
would not go into a board design using more than 90-95% of the pins on
the FPGA. Now if I was updating a mature design or something like that,
I might allow that margin to get a little tighter. The flexibility and
reliability of doing this sort of thing, especially with clocks, inside
the FPGA (where the STA tools can manage your timing) is far superior
to trying to do it with an extra component on the board.
Andy
Elmo Fuchs wrote:
> Hi,
>
> I'm currently developing a PCB featuring a Xilinx Virtex-4 device. Unlinke
> the Virtex-II series they now offer the possibility to route various clock
> signals to several domains on the FPGA and select them locally by specific
> clock multiplexer inputs.
> Because of the restricted amount of available pins on the device I selected
> (Virtex-4 FX40 with 352 user I/Os) I would like to use just one clock input
> on each side of the FPGA, thereby saving clock multiplexer inputs which I
> can use as normal GPIOs, and use an external clock multiplexer instead for
> my 3 clocks.
> Has anyone made experience with such or similar solution? Has anyone used an
> external clock multiplexer device for frequencies up to 500 MHz, yet? Is
> there any recommendation which chip I could use for this application in
> terms of jitter, etc.? And by the way... is my approach advisable, at all?
>
> Any comments are appreciated.
>
> Regards Elmo
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>
> I'm currently developing a PCB featuring a Xilinx Virtex-4 device. Unlinke
> the Virtex-II series they now offer the possibility to route various clock
> signals to several domains on the FPGA and select them locally by specific
> clock multiplexer inputs.
> Because of the restricted amount of available pins on the device I selected
> (Virtex-4 FX40 with 352 user I/Os) I would like to use just one clock input
> on each side of the FPGA, thereby saving clock multiplexer inputs which I
> can use as normal GPIOs, and use an external clock multiplexer instead for
> my 3 clocks.
> Has anyone made experience with such or similar solution? Has anyone used an
> external clock multiplexer device for frequencies up to 500 MHz, yet? Is
> there any recommendation which chip I could use for this application in
> terms of jitter, etc.? And by the way... is my approach advisable, at all?
>
> Any comments are appreciated.
>
> Regards Elmo